Verilog HDL (referred to as Verilog) is a hardware description language used for system design of digital circuits. It can model multiple abstract design levels such as algorithm level, gate level, and switch level.

Verilog inherits many operators and structures from the C language. Compared with another hardware description language VHDL, its syntax is not very strict, the code is more concise, and it is easier to get started.

Verilog not only defines syntax, but also defines clear simulation semantics for syntactic structures. Therefore, digital models written in Verilog can be verified using a Verilog simulator.

Who is this tutorial for?

This tutorial is mainly crafted for Verilog beginners.

Students with some Verilog foundation can also study and exchange ideas on the advanced and example chapters.

Prerequisites for reading this tutorial

Before learning this tutorial, you need to understand some basic information about digital circuits.

If you haveC languagesome understanding of it, it will help you quickly get started with Verilog.

First Verilog Design

4-bit wide decimal counter:

Example

module counter10(
        //Port definitions
        input                   rstn,   //Reset terminal, active low
        input                   clk,    //Input clock
        output [3:0]    cnt,    //Count output
        output                  cout);  //Overflow bit

        reg [3:0]               cnt_temp ;      //Counter register
        always@(posedge clk or negedge rstn) begin
                if(! rstn)begin         //On reset, the count returns to 0
                        cnt_temp        <= 4'b0 ;
                end
                else if (cnt_temp==4'd9) begin  //When counting to 10 cycles, the count returns to 0
                        cnt_temp        <=4'b000;
                end
                else begin                                      //Count increments by 1
                        cnt_temp        <= cnt_temp + 1'b1 ;
                end
        end

        assign  cout = (cnt_temp==4'd9) ;       //Output period bit
        assign  cnt  = cnt_temp ;                       //Output real-time counter

endmodule

Cat Me

I have been engaged in FPGA design and IC design. During my student years, I used VHDL language more for design, but now I have been using Verilog all along. To make it convenient for syntax lookup and to provide a convenient learning channel for other scholars, I specially wrote this tutorial. It should be noted that:

  • (1) The tutorial content is written from the perspective of my own past learning, so it may be easier to learn. If there are any inappropriatenesses, please point them out, and we can exchange ideas and make progress together.
  • (2) When simulating a digital module designed in Verilog, you need to add excitation from outside; the excitation file is called a testbench. Sometimes the testbench design can be more complex than the digital module itself. Therefore, when introducing basic Verilog syntax earlier, there is almost no simulation. Later, when introducing behavior-level and timing-level related knowledge, simulation will be used more for explanation.
<p><strong>Contact email</strong>: [email protected]</p>

Contact person：Think · In · Hardware

The entire tutorial was manually collected, organized, and written by me. All design simulations are original or improved. If you benefit from it, your appreciation or following is the most honest support, encouraging my hungry soul to write fuller chapters.