7.6 Verilog DDS Design
DDS Principle DDS (Direct Digital Synthesis) technology is based on the Nyquist sampling theorem and digital processing technology. It samples a series of analog signals without distortion, stores the resulting digital signals in storage...
8.1 Verilog numeric conversion
This section mainly provides a brief summary of the decimal and binary representations of signed numbers, as well as some numerical transformations. Define a data dbin in two's complement format with width DW. The signed value it represents...
7.5 Verilog FFT Design
FFT (Fast Fourier Transform) is an efficient algorithm for DFT (Discrete Fourier Transform). In digital processing methods based on time-frequency transform analysis, it has an indispensable...
7.4 Verilog CIC Filter Design
Cascaded Integrator Comb (CIC) filter is generally used in digital down-conversion (DDC) and digital up-conversion (DUC) systems. The CIC filter has a simple structure, no multipliers, only...
7.3 Verilog Serial FIR Filter Design
Serial FIR Filter Design Design Description The design parameters remain unchanged and are consistent with the parallel FIR filter parameters. That is, the input is a mixed sinusoidal signal with frequencies of 7.5 MHz and 250 kHz. After passing through the FIR...
7.2 Verilog Parallel FIR Filter Design
FIR (Finite Impulse Response) filter is a finite-length unit impulse response filter, also known as a non-recursive filter. The FIR filter has strict linear phase-frequency characteristics, and its unit...
7.1 Verilog Divider Design
Divider Principle (Fixed-Point) Similar to decimal division, the process of calculating 27 divided by 5 is as follows: The division operation process is as follows: (1) Take the high-order bits of the dividend, with a bit width equal to the divisor...
6.7 Verilog Pipeline
Keywords: pipeline, multiplier. A prominent advantage of hardware description languages is the parallelism of instruction execution. Multiple statements can process multiple signal data in parallel within the same clock cycle. However, when data...
6.6 Verilog simulation stimulus
Keywords: testbench, simulation, file read/write After the Verilog code design is completed, an important step remains: logic function simulation. The simulation stimulus file is called testbench, placed in each...
6.5 Verilog: Avoiding Latches
Keywords: flip-flop, latch Meaning of Latch A latch is a level-triggered storage unit. The data storage operation depends on the level value of the input clock (or enable) signal. Only...