Verilog has strong circuit description and modeling capabilities, and can describe and model digital systems at multiple levels. Therefore, it has shown strong vitality and potential in simplifying hardware design tasks, improving design efficiency and reliability, language readability, hierarchical and structured design, and other aspects.

Development History

  • In 1983, Verilog was originally created by Phil Moorby of Gateway Design Automation (GDA) as the language for an internal simulator, mainly used for logic modeling and simulation verification, and was widely used.
  • In 1989, GDA was acquired by Cadence, and the Verilog language became the private property of Cadence.
  • In 1990, Cadence established the OVI (Open Verilog International) organization, made the Verilog language public, and promoted the development of Verilog into the public domain.
  • In 1992, OVI decided to dedicate itself to promoting the Verilog OVI standard as an IEEE (The Institute of Electrical and Electronics Engineers) standard.
  • In 1995, OVI's efforts were successful; IEEE established the first international standard for Verilog HDL, namely IEEE Std 1364-1995, also called Verilog 1.0.
  • In 2001, IEEE released the second Verilog standard (Verilog 2.0), namely IEEE Std 1364-2001, referred to as the Verilog-2001 standard. Due to Cadence's influence in the field of integrated circuit design and the simplicity and ease of use of the Verilog language, Verilog became the most popular hardware description language in circuit design.

Main Features

The following are the main features of Verilog:

  • Design modeling can be performed in 3 different ways: behavioral-level description — modeling using procedural structures; dataflow description — modeling using continuous assignment statements; structural style — description using gate and module instantiation statements.
  • Two types of data: the net (wire) data type and the register (reg) data type; nets represent wires between physical components, and registers represent abstract data storage elements.
  • It can describe hierarchical designs; module instantiation can be used to describe any hierarchy.
  • User-defined primitives (UDP) are very flexible to create. Primitives can be either combinational logic or sequential logic.
  • It can provide explicit language constructs to specify port-to-port delays in a design, as well as path delays and timing checks.
  • Verilog supports the Programming Language Interface (PLI) for further expansion. PLI allows external functions to access internal information of Verilog modules, providing richer testing methods for simulation.
  • The same language can be used to generate simulation stimuli and specify test constraints.
  • When designing logic functions, designers do not need to care about factors that do not affect the logic function, such as process, temperature, etc.
  • ……

Main Applications

Application-specific integrated circuit (ASIC) is an independent integrated circuit device with specific purposes and special functions.

As a hardware description language, Verilog is mainly used to generate application-specific integrated circuits.

This is mainly accomplished through 3 approaches:

1. Programmable Logic Devices

FPGAs and CPLDs are the mainstream devices for this approach. They are directly user-oriented, have great flexibility and versatility, are quick to implement, easy to test, and offer high development efficiency with lower cost.

2. Semi-custom or Full-custom ASIC

In layman's terms, it is the use of Verilog to design dedicated chips with certain special functions. According to differences in the processes of basic cells, they can be further divided into gate array ASIC, standard cell ASIC, and full-custom ASIC.

3. Mixed ASIC

It mainly refers to devices that have both user-oriented FPGA programmable logic functions and logic resources, and also contain hardware standard cell modules that can be conveniently invoked and configured, such as CPU, RAM, phase-locked loops, multipliers, etc.