Value Types

Verilog HDL has the following four basic values to represent logic levels in hardware circuits:

  • 0: Logic 0 or 'false'
  • 1: Logic 1 or 'true'
  • x or X: Unknown
  • z or Z: High impedance

xMeans the value of the signal is uncertain, that is, in an actual circuit, the signal may be 1 or 0.

zMeans the signal is in a high-impedance state, commonly seen as the logic result when a signal (input, reg) is not driven. For example, when an input of a pad is in a high-impedance state, its logic value is related to the pull-up/pull-down state. If pulled up, the logic value is 1; if pulled down, it is 0.

Integer Value Representation

When declaring numbers, there are 4 legal base formats, including: decimal ('d or 'D), hexadecimal ('h or 'H), binary ('b or 'B), octal ('o or 'O). The value can specify the bit width, or it can be unspecified.

Specifying bit width:

Example

4'b1011         // 4bit value
32'h3022_c0de   // 32bit value

Among them, the underscore_is used to enhance code readability.

Without specifying bit width:

Generally, when writing numbers directly, decimal representation is the default. For example, the following 3 writing methods are equivalent:

Example

counter = 'd100 ; // Generally, the bit width is automatically allocated by the compiler, commonly 32bit
counter = 100 ;
counter = 32'h64 ;

Negative Number Representation

Usually, a minus sign is added before the number indicating the bit width to represent a negative number. For example:

-6'd15  
-15

-15 in 5-bit binary is 5'b10001, and in 6-bit binary it is 6'b11_0001.

It should be noted that placing the minus sign between the base and the number is illegal. For example, the following representation is wrong:

4'd-2 //非法说明

Real Number Representation

There are mainly two ways to represent real numbers:

Decimal:

30.123
6.0
3.0
0.001

Scientific notation:

1.2e4         //大小为12000
1_0001e4      //大小为100010000
1E-3          //大小为0.001

String Representation

A string is a sequence of characters enclosed in double quotes. A string cannot be written over multiple lines, meaning it cannot contain carriage return characters. Verilog treats strings as a sequence of single-byte ASCII characters. For example, to store the string "www.example.com", 14*8bit of storage units are needed. For example:

Example

reg [0: 14*8-1]       str ;
initial begin
    str = "www.example.com";
end