The built-in gate units introduced in gate-level modeling, such as and, or, nor, etc., all belong to a complete set of standard primitives that come with Verilog, commonly known as built-in primitives.

In addition, Verilog also provides users with the ability to write their own primitives. Such primitives are called User Defined Primitives (UDP for short).

In a UDP, other modules or primitives cannot be called. The invocation method is exactly the same as that of gate-level primitives.

There are mainly the following 2 types of UDP, which will be introduced one by one later.

  • Combinational logic UDP: the output depends only on the combinational logic of the input signals.
  • Sequential logic UDP: the next output value depends not only on the current input value, but also on the current internal state.

UDP Definition

The definition of a UDP does not depend on a module definition, so it can appear outside a module definition, or be defined separately in a file.

The UDP format is defined as follows:

Example

primitive UDP_name (
  output_name,
  list_of_input) ;

  output_declaration ;
  list_of_input_declaration ;
  [reg_declaration] ;
  [initial_statement] ;
 
  table
    list_of_table_entries ;
  endtable
endprimitive

UDP Description

Port declaration:

  • 1. The port declaration part is similar to a module. You can either list only the port signals in the port list declaration and then specify their types in the primitive body, or directly specify their types in the port list declaration.
  • 2. Input ports can only be scalars (i.e., 1 bit), and multiple input ports are allowed.
  • 3. Only one scalar output port (i.e., 1 bit) is allowed, and the output port must appear in the first position of the port list. Multiple output ports are absolutely not allowed.
  • 4. The output port is declared with the output keyword. Since a sequential logic UDP needs to store state, its output port must also be declared as reg type.
  • 5. UDP does not support the inout port type.

Initialization

An initial statement can be used to initialize the output port (reg type) of a sequential logic UDP. This statement is optional.

State Table

  • 1. The UDP state table is the most important part of a UDP. It is declared with the keyword table and defines how to obtain the output value based on the input state and current state, similar to a logic truth table.
  • 2. Entries in the state table can be 0, 1, or x. UDP cannot handle z values, so z values passed to a UDP are treated as x.